Design Engineer V (ASIC Power Engineer)
Overview
We are seeking a senior?level ASIC Power Engineer to support advanced silicon development for next?generation AR/VR products. This role focuses on power analysis, optimization, and low?power design across RTL through backend flows in a fast?paced, highly technical environment.
This is a high?impact opportunity for a dedicated power expert who enjoys deep technical ownership and collaboration across hardware and software teams.
Details
- Location: Sunnyvale, CA (Hybrid)
- Duration: 6 month contract
- Pay Rate: Up to $185/hour
- Schedule: Standard business hours
Responsibilities
- Perform power, performance, and area (PPA) optimization using industry?standard tools
- Conduct RTL? and netlist?level power analysis
- Run, debug, and analyze ASIC flows including synthesis, physical design, power, and timing
- Develop and maintain scripts for report post?processing, data analysis, and automation
- Implement select blocks at RTL and UPF
- Analyze power tradeoffs across design and backend implementation
- Clearly document findings and communicate results to cross?functional teams
Required Qualifications
- 10+ years of experience as an ASIC Power Engineer, CAD Engineer, or Physical Design Engineer
- Strong hands?on experience with power estimation and optimization tools
- Expertise in low?power design methodologies, including UPF power intent
- Proficiency in Python, Perl, TCL, or similar scripting languages
- Solid understanding of power tradeoffs in ASIC design and implementation
- Bachelor’s degree in Electrical Engineering, Computer Science, or equivalent experience
Preferred Qualifications
- Experience with Synopsys tools (DC, ICC, PrimePower/PTPX, VCS, Verdi) and/or Cadence Joules
- Experience with silicon power characterization
- Power profiling experience at the IP or SoC level
- Strong data analysis and visualization skills (Excel, MATLAB, or similar)
- Background supporting advanced silicon for consumer or embedded products
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